1. Field of the Invention
The present invention relates to the field of microelectronics. It relates to the field of the production of planar structures.
2. Description of the Related Technology
A typical electrostatic capacitive RF-MEMS device shown in FIG. 1 comprises a free-standing metal armature 100, hereafter called bridge, overlapping with a fixed metal actuation electrode 102. The actuation electrode 102 is covered with a dielectric layer 104 that is contacted upon actuation of the device.
When designing such a structure, various parameters have to be taken into account. Some parameters are listed in Table 1.
TABLE 1Design parameters for an RF-MEMS deviceSpring constantkResonance frequencyfresPull-in voltageVPIPull-out voltageVPOUp-state capacitanceCupDown-state capacitanceCdown
The parameters k, fres, VP1 and VPO are linked to the actuation of the device while the parameters CUP and CDOWN are linked to the RF-application.
In practice, the parameters listed in Table 1 are not properly defined. The realized devices have inconsistent resonance frequencies, pull-in and pull-out voltages that can be related to an inconsistent spring constant of the armature. While Cup is in general reasonably defined in case of clamped-clamped armatures, i.e. bridge 100, Cdown is constantly ill-defined, i.e. much lower than its target value. These uncertainties can all be related to an uncertain definition of the shape of the bridge 100.
The definition of Cdown for example is representative of the contact quality between the actuated bridge 100 and the underlying fixed dielectric layer 104. At the micro-level, this contact quality is degraded by the roughness of the dielectric layer 104 and of the bridge 100 [X. Rottenberg, H. Jansen, P. Fiorini, W. De Raedt and H. A. C. Tilmans, “Novel RF-MEMS capacitive switching structures”, proc. 32nd European Microwave Conference, pp. 809-812, Milan, Italy, 23-27 Sep., 2002]. At the macro-level, the intimate contact between bridge 100 and dielectric layer 104 is degraded by the non-planarity of the bridge layer as shown in FIG. 2 [U.S. patent application US-2003/129843, Cai, Y. and Katehi L. P. B. “Planarizing recess etch”]. This macro-non-planarity is due to the poor topography absorption of the sacrificial layer used as a support for the bridge layer.
To obtain an intimate contact between bridge 100 and dielectric layers 104 when the device is closed, the bridge 100 may not touch anything on its way down before it touches the surface of the dielectric layer 104. The uncontrolled non-planarity of the armature 100 allows for parasitic contacts at the edge of the actuation electrode 102 or at the edge of any profile lying under the bridge layer. These can stop the bridge 100 on its way towards the dielectric 104 and prevent the good definition of Cdown as demonstrated by Yu, et al. in “Improvement of isolation for MEMS capacitive switch via membrane planarisation”.
In order to define a predictable technology, a process flow offering consistently flat bridges is clearly preferred. A second choice, fall-back and less preferred, would be a process flow that defines bridges with the inverse profile of the underlying topography, i.e. hills above valleys.
Currently, relying only on the topography absorption of the sacrificial layer forces to limit the thickness of the layers under the bridges to a few hundreds of nanometers what introduces large conductive losses at low frequencies, i.e. in the few GHz range.
Further, flat bridges (or with controlled profile) are much easier to model as their k, fres, VP1 and VPO are better defined.
Several planarization improvement schemes have already been proposed. A first scheme for planarizing the bridges is to deposit a bloc of sacrificial layer in the valleys of the existing topographies before applying the actual sacrificial layer and defining the bridges. The total sacrificial layer is thus deposited in 2 steps. To do that, a special mask has to be used. The alignment and definition of the “filling layer”, i.e. that part of the sacrificial layer filling the valleys between the topographies, are critical. In practice, it is impossible to fully fill the valleys as a few microns misalignment always have to be allowed in order for the filling layer to fit in the valleys.
The main improvement brought by this solution is that the gap to be filled is standardized. Any valleys, designed for example for RF purpose, will be transformed by gap-filling into a standard for example 5 micron wide gap defined by the process accuracy. The process flow further relies on the aptitude of the actual sacrificial layer to planarize this gap.
A typical process flow for this technique is shown in FIG. 3 taken from Yu, et al. “Improvement of isolation for MEMS capacitive switch via membrane planarisation”.
A second scheme proposed by Cai and Katehi [US-2003/129843] is to embed the underlying profile in the substrate before depositing the sacrificial layer and bridges, as shown in FIG. 4.
The advantage of this technique is that the same mask can be used to etch the holes in the substrate and to deposit the underlying profiles, e.g. CPW lines (CoPlanar Waveguide), mimicking a lift off deposition process. This deposition delivers almost flat wafers. Nevertheless, parasitic gaps still remain. This time, there is no misalignment but well an undercut of the substrate due to the process used to define the holes.
Of course this technique relies on the accurate patternability of the substrate. This is not obvious in the case of glass wafers for example, often used for RF circuitry. Further, in the case of Si or other lossy substrates, the embedding of the lines in the substrate is not a preferred situation for what the losses concerns.
It is further not obvious whether this technique offers really a solution to the Cdown definition problem as even perfectly flat bridges could be stopped by the remaining substrate studs protruding above the topography. The substrate is indeed in general not attacked by the sacrificial layer removal step.
The sacrificial layer used in thin film MEMS devices is often a photosensitive polymer that is spun or sprayed on the wafer before the bridge definition. When this polymer is applied, it is in a fluid solution mixed with a solvent. During the spinning/spraying, the solvent evaporates, what changes the viscosity of the solution and thus its planarization characteristic. In a third scheme the step coverage of the sacrificial layer is improved by spraying on the sacrificial layer a small amount of solvent or by applying an appropriate temperature profile that allows the sacrificial layer to get temporarily more fluid and reflow it after its deposition. It works only partially. The sacrificial layer can form further lenticular shapes on the high areas due to the capillary forces.
A fourth scheme, based on Chemical Mechanical Polishing (CMP) is in principle the most straightforward. Reproducibly polishing a polymer sacrificial layer down to a controlled thickness is nevertheless rather difficult. Further, the price for implementing this technique is the too prohibitive for the major RF-MEMS and purely MEMS target applications.
It is thus desirable to provide for a method for producing of structures with a flat upper surface, which alleviates or avoids the problems of the prior art.